(1) Field of the Invention
This invention relates to high voltage MOS, metal oxide semiconductor, devices and methods of forming MOS devices, and more particularly to high voltage MOS devices which do not require a deep n type silicon well or p type silicon well.
(2) Field of the Invention
It is frequently desirable to fabricate high voltage metal oxide semiconductor, MOS, devices. These devices typically use lightly doped drift regions adjacent to more heavily doped drain regions to suppress the onset of avalanche multiplication. These devices also typically use an n well or p well having increased depth.
U.S. Pat. No. 4,232,327 to Hsu and U.S. Pat. No. 5,512,495 to Mei et al. describes high voltage MOSFETs, metal oxide semiconductor field effect transistors, using a lightly doped drift region adjacent to a more heavily doped drain.
U.S. Pat. No. 6,133,107 to Menegoli and U.S. Pat. No. 5,591,675 to Fujishima et al. describe high voltage MOSFETs using deep well regions.
It is frequently desirable to form standard voltage N channel or P channel metal oxide semiconductor and high voltage N channel metal oxide semiconductor devices on the same chip or wafer. This is not possible if the high voltage P channel device requires a deep n well. FIG. 1 shows a cross section view of a high voltage P channel device. A lightly doped epitaxial layer 12 of pxe2x88x92 type silicon is formed over a substrate 10 of heavily doped p+ type silicon. The lightly doped well 13 of nxe2x88x92 type silicon, in which the high voltage device is formed, has a depth 28 larger than that for a typical device. This results in a smaller gap 30 between the bottom of the well 13 and the substrate 10. The typical high voltage device shown in FIG. 1 has a p+ type source 16 on one side of the channel, a pxe2x88x92 type drift region 20 on the other side of the channel, and a p+ type drain adjacent to the drift region 20. The device shown in FIG. 1 also has a thick oxide 22A overlaying the drift region 20, thick oxide isolation regions 22B, a gate oxide layer 26, and a gate electrode 24.
The depth 28 of the well is a critical factor in determining the operating voltage of the high voltage P channel device. If the well 13 is too deep the well to substrate gap 30 will be too small which will reduce the maximum operating voltage available. If the well 13 is too shallow punch-through from the P channel drain 18 through the drift region 20 into the substrate 10 will occur. The formation of a deep well of n type silicon is typically formed using a Phosphorous implant followed by a long thermal drive in. This thermal drive in has the undesirable effect of enhancing diffusion of impurities from the p+ substrate 10 into the pxe2x88x92 epitaxial layer. This requires a thicker pxe2x88x92 epitaxial layer which will degrade the latch-up immunity of standard CMOS devices, causing problems for integrating high voltage devices and standard devices in the same chip or wafer.
It is a principle objective of this invention to provide a method of forming high voltage metal oxide semiconductor P channel devices without increasing the depth of the well of n type silicon in which the high voltage devices are located and which can be integrated on the same chip or wafer with standard metal oxide semiconductor devices.
It is another principle objective of this invention to provide high voltage metal oxide semiconductor P channel devices having a standard depth of the well of n type silicon in which the high voltage devices are located and which can be integrated on the same chip or wafer with standard metal oxide semiconductor devices.
These objectives are achieved by implanting a high voltage support region 44, see FIG. 2, directly below the drift region 20. The high voltage support region is doped to be heavily doped n type silicon, n+ type silicon. A higher energy implanter than that used in forming other doped regions is used to locate the high voltage support region directly below the drift region 20. This high voltage support region avoids punch-through from the P channel drain 18 through the drift region 20 into the substrate 10 while using a standard depth for the n type well 14, see FIG. 2.